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Hiroyuki Yamauchi

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2007
11EEHiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami: A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Transactions 90-C(4): 749-757 (2007)
10EEYasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi: A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Transactions 90-C(5): 1129-1137 (2007)
2006
9EEHiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami: A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. IEICE Transactions 89-C(11): 1526-1534 (2006)
2005
8EEToshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi: 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Transactions 88-C(4): 630-638 (2005)
2000
7EEHiroyuki Yamauchi, Setsuo Ohsuga: A Method and Language for Constructing Multiagent Systems. ISMIS 2000: 619-628
1999
6 Hiroyuki Yamauchi, Setsuo Ohsuga: Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration. RSFDGrC 1999: 304-313
1997
5EEHiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa: A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. VLSI Syst. 5(4): 377-387 (1997)
1996
4EEHiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa: A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED 1996: 49-54
1990
3 Hiroyuki Yamauchi, Setsuo Ohsuga: Losse Coupling of KAUS with Existing RDBMSs. Data Knowl. Eng. 5: 227-251 (1990)
1985
2 Setsuo Ohsuga, Hiroyuki Yamauchi: Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language. New Generation Comput. 3(4): 403-439 (1985)
1980
1EEHiroyuki Yamauchi: Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic. COLING 1980: 389-396

Coauthor Index

1Yasuhiro Agata [10]
2Hironori Akamatsu [4] [5] [8]
3Ichiro Hatanaka [8]
4Toru Iwata [4] [5]
5Toshiaki Kawasaki [10]
6Hirohito Kikukawa [10]
7Akira Matsuzawa [4] [5]
8Ryuji Nishihara [10]
9Setsuo Ohsuga [2] [3] [6] [7]
10Akinori Shibayama [8]
11Masanori Shirahama [10]
12Shinichi Sumi [10]
13Toshikazu Suzuki [8] [9] [11]
14Yoshinobu Yamagami [8] [9] [11]
15Yasue Yamamoto [10]

Colors in the list of coauthors

Copyright © Thu Jun 5 01:14:00 2008 by Michael Ley (ley@uni-trier.de)