Xiaojun Wang

2008
15	EE	Xiaojun Wang, Miriam Leeser: Efficient FPGA implementation of qr decomposition using a systolic array architecture. FPGA 2008: 260
2006
14	EE	Xiaojun Wang, Xiaofeng Zhou: Application and Integration of Information Technology in Water Resources Informatization. APWeb 2006: 1004-1009
13	EE	Xiaojun Wang, Sherman Braganza, Miriam Leeser: Advanced Components in the Variable Precision Floating-Point Library. FCCM 2006: 249-258
12	EE	Xin Zhang, Bin Liu, Wei Li, Y. Xi, D. Bermingham, Xiaojun Wang: IPv6-Oriented 4*OC768 Packet Classification with Deriving-Merging Partition and Field-Variable Encoding Algorithm. INFOCOM 2006
2004
11		Li-Chuan Weng, Xiaojun Wang, Alan P. Su, Bin Liu: Low Power Heuristic Block-level Voltage/Frequency Scheduling. ESA/VLSI 2004: 577-581
2003
10	EE	Xiaojun Wang, Brent E. Nelson: Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. FCCM 2003: 195-
9	EE	Li-Chuan Weng, Xiaojun Wang, Bin Liu: A Survey of Dynamic Power Optimization Techniques. IWSOC 2003: 48-52
2001
8	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. IEEE International Workshop on Rapid System Prototyping 2001: 162-167
7	EE	V. Muresan, Xiaojun Wang, Mircea Vladutiu: A combined tree growing technique for block-test scheduling under power constraints. ISCAS (5) 2001: 255-258
2000
6	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Asian Test Symposium 2000: 465-470
5	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Power-Constrained Block-Test List Scheduling. IEEE International Workshop on Rapid System Prototyping 2000: 182-187
4	EE	Jin Ding, David Moloney, Xiaojun Wang: Aliasing-Free Space and Time Compactions with Limited Overhead. ISQED 2000: 355-360
3		Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: A comparison of classical scheduling approaches in power-constrained block-test scheduling. ITC 2000: 882-891
2	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. VTS 2000: 417-422
1998
1	EE	Gregory D. Speegle, Xiaojun Wang, Le Gruenwald: A Meta-Structure for Supporting Multimedia Editing in Object-Oriented Databases. BNCOD 1998: 89-102

Coauthor Index

1	D. Bermingham	[12]
2	Sherman Braganza	[13]
3	Jin Ding	[4]
4	Le Gruenwald	[1]
5	Miriam Leeser	[13] [15]
6	Wei Li	[12]
7	Bin Liu	[9] [11] [12]
8	David Moloney	[4]
9	V. Muresan	[7]
10	Valentin Muresan	[2] [3] [5] [6] [8]
11	Valentina Muresan	[2] [3] [5] [6] [8]
12	Brent E. Nelson	[10]
13	Gregory D. Speegle	[1]
14	Alan P. Su	[11]
15	Mircea Vladutiu	[2] [3] [5] [6] [7] [8]
16	Li-Chuan Weng	[9] [11]
17	Y. Xi	[12]
18	Xin Zhang	[12]
19	Xiaofeng Zhou	[14]

Colors in the list of coauthors