
| 2003 | ||
|---|---|---|
| 35 | EE | Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton: Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) |
| 34 | EE | Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design 22(3): 205-224 (2003) |
| 33 | EE | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz: An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. Formal Methods in System Design 23(1): 39-65 (2003) |
| 2002 | ||
| 32 | Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods in System Design 21(2): 193-224 (2002) | |
| 2001 | ||
| 31 | EE | Tai-Hung Liu, Adnan Aziz, Vigyan Singhal: Optimizing designs containing black boxes. ACM Trans. Design Autom. Electr. Syst. 6(4): 591-601 (2001) |
| 30 | EE | Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Theory of safe replacements for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001) |
| 2000 | ||
| 29 | Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming Andersen: An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. CAV 2000: 5-19 | |
| 28 | EE | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDS: a BDD-based logic optimization system. DAC 2000: 92-97 |
| 27 | EE | Praveen Yalagandula, Adnan Aziz, Vigyan Singhal: Automatic Lighthouse Generation for Directed State Space Search. DATE 2000: 237-242 |
| 26 | EE | Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Model-checking continous-time Markov chains. ACM Trans. Comput. Log. 1(1): 162-170 (2000) |
| 1999 | ||
| 25 | EE | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz: Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. CAV 1999: 72-83 |
| 24 | EE | Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton: Using Combinational Verification for Sequential Circuits. DATE 1999: 138-144 |
| 23 | EE | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDD Decomposition for Efficient Logic Synthesis. ICCD 1999: 626- |
| 22 | EE | Carl Pixley, Vigyan Singhal: Model Checking: A Hardware Design Perspective. STTT 2(3): 288-306 (1999) |
| 1998 | ||
| 21 | Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255 | |
| 20 | EE | Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton: On the optimization power of retiming and resynthesis transformations. ICCAD 1998: 402-407 |
| 19 | EE | Jerry R. Burch, Vigyan Singhal: Robust latch mapping for combinational equivalence checking. ICCAD 1998: 563-569 |
| 18 | EE | Jerry R. Burch, Vigyan Singhal: Tight integration of combinational verification methods. ICCAD 1998: 570-576 |
| 1997 | ||
| 17 | EE | Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal: Optimizing Designs Containing Black Boxes. DAC 1997: 113-116 |
| 16 | EE | Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli: Sequential optimisation without state space exploration. ICCAD 1997: 208-215 |
| 15 | EE | Vigyan Singhal, Alan Jay Smith: Analysis of Locking Behavior in Three Real Database Systems. VLDB J. 6(1): 40-52 (1997) |
| 1996 | ||
| 14 | Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Verifying Continuous Time Markov Chains. CAV 1996: 269-276 | |
| 13 | EE | Vigyan Singhal, Sharad Malik, Robert K. Brayton: The case for retiming with explicit reset circuitry. ICCAD 1996: 618-625 |
| 12 | EE | Shaz Qadeer, Robert K. Brayton, Vigyan Singhal: Latch Redundancy Removal Without Global Reset. ICCD 1996: 432-439 |
| 1995 | ||
| 11 | Adnan Aziz, Vigyan Singhal, Felice Balarin: It Usually Works: The Temporal Logic of Stochastic Systems. CAV 1995: 155-165 | |
| 10 | EE | Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton: The Validity of Retiming Sequential Circuits. DAC 1995: 316-321 |
| 9 | EE | Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal: Incremental methods for FSM traversal. ICCD 1995: 590- |
| 8 | Vigyan Singhal, Robert K. Brayton, Carl Pixley: Power-Up Delay for Retiming Digital Circuits. ISCAS 1995: 566-569 | |
| 1994 | ||
| 7 | Vigyan Singhal, Carl Pixley: The Verifiacation Problem for Safe Replaceability. CAV 1994: 311-323 | |
| 6 | Adnan Aziz, Thomas R. Shiple, Vigyan Singhal: Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV 1994: 324-337 | |
| 5 | EE | Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 |
| 4 | Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalences for Fair Kripke Structures. ICALP 1994: 364-375 | |
| 3 | EE | Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton: Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449 |
| 2 | Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton: Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261 | |
| 1993 | ||
| 1 | Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton: Heuristic Minimization of Synchronous Relations. ICCD 1993: 428-433 | |
Colors in the list of coauthors