Aviral Shrivastava

2008
22	EE	Aviral Shrivastava, Ilya Issenin, Nikil Dutt: A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. ASP-DAC 2008: 328-333
21	EE	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek: SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. ASP-DAC 2008: 776-782
20	EE	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi: PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. VLSI Design 2008: 421-427
19	EE	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520
18	EE	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma Vrudhul: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539
2007
17	EE	Michael A. Baker, Aviral Shrivastava, Karam S. Chatha: Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS 2007: 197-202
16	EE	Qiang Zhu, Aviral Shrivastava, Nikil Dutt: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. DATE 2007: 1164-1169
15	EE	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek: Automatic Design Space Exploration of Register Bypasses in Embedded Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2102-2115 (2007)
2006
14	EE	Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian: Mitigating soft error failures for multimedia applications by selective data protection. CASES 2006: 411-420
13	EE	Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek: Automatic generation of operation tables for fast exploration of bypasses in embedded processors. DATE 2006: 1197-1202
12	EE	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Bypass aware instruction scheduling for register file power reduction. LCTES 2006: 173-181
11	EE	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ACM Trans. Design Autom. Electr. Syst. 11(1): 123-146 (2006)
10	EE	Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006)
9	EE	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Retargetable pipeline hazard detection for partially bypassed processors. IEEE Trans. VLSI Syst. 14(8): 791-801 (2006)
2005
8	EE	Aviral Shrivastava, Ilya Issenin, Nikil Dutt: Compilation techniques for energy reduction in horizontally partitioned cache architectures. CASES 2005: 90-96
7	EE	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Aggregating processor free time for energy reduction. CODES+ISSS 2005: 154-159
6	EE	Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. DATE 2005: 1264-1269
2004
5	EE	Aviral Shrivastava, Nikil D. Dutt: Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). ASP-DAC 2004: 475-477
4	EE	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Operation tables for scheduling in the presence of incomplete bypassing. CODES+ISSS 2004: 194-199
2002
3	EE	Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. DATE 2002: 402-408
2	EE	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi: A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ISSS 2002: 120-125
2000
1	EE	Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan: Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113

Coauthor Index

1	Minwook Ahn	[21]
2	Michael A. Baker	[17]
3	M. Balakrishnan	[1]
4	Sarvesh Bhardwaj	[18] [19]
5	Partha Biswas	[2] [3] [11]
6	Karam S. Chatha	[17]
7	Nikil D. Dutt (Nikil Dutt)	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [20] [22]
8	Eugene Earlie	[4] [6] [7] [9] [12] [13] [15]
9	Aseem Gupta	[20]
10	Ashok Halambi	[2] [3] [11]
11	Ilya Issenin	[8] [14] [22]
12	Reiley Jeyapaul	[21]
13	Deepa Kannan	[18] [19] [20]
14	Sanjiv Kapoor	[1]
15	Mohit Kumar	[1]
16	Shashi Kumar	[1]
17	Fadi J. Kurdahi	[20]
18	Kyoungwoo Lee	[14]
19	Prabhat Mishra	[10]
20	Vipin Mohan	[19]
21	Alexandru Nicolau (Alex Nicolau)	[2] [3] [4] [6] [7] [9] [11] [12] [13] [15]
22	Yunheung Paek	[12] [13] [15] [21]
23	Sanghyun Park	[12] [13] [15] [21]
24	Nalini Venkatasubramanian	[14]
25	Sarma Vrudhul	[18]
26	Sarma B. K. Vrudhula	[19]
27	Jonghee W. Yoon	[21]
28	Qiang Zhu	[16]

Colors in the list of coauthors