| 2007 |
| 47 | EE | Hiroshi Sasaki,
Yoshimichi Ikeda,
Masaaki Kondo,
Hiroshi Nakamura:
An intra-task dvfs technique based on statistical analysis of hardware events.
Conf. Computing Frontiers 2007: 123-130 |
| 46 | EE | Ryo Watanabe,
Masaaki Kondo,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
DATE 2007: 797-802 |
| 45 | EE | Hiroshi Nakamura:
Fast Abstracts.
DSN 2007: 812 |
| 44 | EE | Masaaki Kondo,
Yoshimichi Ikeda,
Hiroshi Nakamura:
A High Performance Cluster System Design by Adaptie Power Control.
IPDPS 2007: 1-8 |
| 43 | EE | Takeshi Mishima,
Hiroshi Nakamura:
A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control.
PRDC 2007: 334-337 |
| 2006 |
| 42 | EE | Taisuke Boku,
Mitsuhisa Sato,
Daisuke Takahashi,
Hiroshi Nakashima,
Hiroshi Nakamura,
Satoshi Matsuoka,
Yoshihiko Hotta:
MegaProto/E: power-aware high-performance cluster with commodity technology.
IPDPS 2006 |
| 41 | EE | Hiroshi Sasaki,
Masaaki Kondo,
Hiroshi Nakamura:
Energy-efficient dynamic instruction scheduling logic through instruction grouping.
ISLPED 2006: 43-48 |
| 40 | EE | Kohji Itoh,
Hiroshi Nakamura,
Shunsuke Unno,
Jun'ichi Kakegawa:
A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions.
KES (2) 2006: 1071-1078 |
| 39 | EE | Kouichi Watanabe,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura,
Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Transactions 89-A(12): 3519-3528 (2006) |
| 2005 |
| 38 | EE | Ken-ichi Kurata,
Hiroshi Nakamura,
Vincent Breton:
Secret sequence comparison on public grid computing resources.
CCGRID 2005: 832-839 |
| 37 | EE | Masaaki Kondo,
Hiroshi Nakamura:
A Small, Fast and Low-Power Register File by Bit-Partitioning.
HPCA 2005: 40-49 |
| 36 | EE | Hiroshi Nakashima,
Hiroshi Nakamura,
Mitsuhisa Sato,
Taisuke Boku,
Satoshi Matsuoka,
Daisuke Takahashi,
Yoshihiko Hotta:
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.
IPDPS 2005 |
| 35 | EE | Hiroshi Sasaki,
Masaaki Kondo,
Hiroshi Nakamura:
Dynamic Instruction Cascading on GALS Microprocessors.
PATMOS 2005: 30-39 |
| 34 | EE | Hiroshi Nakashima,
Hiroshi Nakamura,
Mitsuhisa Sato,
Taisuke Boku,
Satoshi Matsuoka,
Daisuke Takahashi,
Yoshihiko Hotta:
MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology.
SC 2005: 28 |
| 33 | EE | Daisuke Komura,
Hiroshi Nakamura,
Shuichi Tsutsumi,
Hiroyuki Aburatani,
Sigeo Ihara:
Multidimensional support vector machines for visualization of gene expression data.
Bioinformatics 21(4): 439-444 (2005) |
| 2004 |
| 32 | EE | Motonobu Fujita,
Masaaki Kondo,
Hiroshi Nakamura:
Data Movement Optimization for Software-Controlled On-Chip Memory.
Interaction between Compilers and Computer Architectures 2004: 120-127 |
| 31 | EE | Masaaki Kondo,
Hiroshi Nakamura:
Dynamic Processor Throttling for Power Efficient Computations.
PACS 2004: 120-134 |
| 30 | EE | Daisuke Komura,
Hiroshi Nakamura,
Shuichi Tsutsumi,
Hiroyuki Aburatani,
Sigeo Ihara:
Multidimensional support vector machines for visualization of gene expression data.
SAC 2004: 175-179 |
| 29 | EE | Hiroshi Nakamura,
Takuro Hayashida,
Masaaki Kondo,
Yuya Tajima,
Masashi Imai,
Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures.
SRDS 2004: 116-125 |
| 28 | EE | Chikafumi Takahashi,
Masaaki Kondo,
Taisuke Boku,
Daisuke Takahashi,
Hiroshi Nakamura,
Mitsuhisa Sato:
SCIMA-SMP: on-chip memory processor architecture for SMP.
WMPI 2004: 121-128 |
| 27 | EE | Nicolas Jacq,
Christophe Blanchet,
Christophe Combet,
E. Cornillot,
Laurent Duret,
Ken-ichi Kurata,
Hiroshi Nakamura,
T. Silvestre,
Vincent Breton:
Grid as a bioinformatic tool.
Parallel Computing 30(9-10): 1093-1107 (2004) |
| 2003 |
| 26 | EE | Hiroshi Saito,
Euiseok Kim,
Nattha Sretasereekul,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.
ASYNC 2003: 184-195 |
| 25 | EE | Ken-ichi Kurata,
Vincent Breton,
Hiroshi Nakamura:
A Method to Find Uniq e Sequences on Distrib ted Genomic Databases.
CCGRID 2003: 62-69 |
| 24 | EE | Euiseok Kim,
Hiroshi Saito,
Jeong-Gun Lee,
Dong-Ik Lee,
Hiroshi Nakamura,
Takashi Nanya:
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.
DATE 2003: 10276-10281 |
| 23 | EE | Nattha Sretasereekul,
Hiroshi Saito,
Masashi Imai,
Euiseok Kim,
Metehan Özcan,
K. Thongnoo,
Hiroshi Nakamura,
Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller.
ISCAS (5) 2003: 205-208 |
| 22 | EE | Hiroshi Saito,
Euiseok Kim,
Masashi Imai,
Nattha Sretasereekul,
Hiroshi Nakamura,
Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information.
ISCAS (5) 2003: 617-620 |
| 2002 |
| 21 | EE | Masaaki Kondo,
Mitsugu Iwamoto,
Hiroshi Nakamura:
Cache Line Impact on 3D PDE Solvers.
ISHPC 2002: 301-309 |
| 20 | | Hiroshi Saito,
Hiroshi Nakamura,
Masahiro Fujita,
Takashi Nanya:
Logic Optimization for Asynchronous SI Controllers using Transduction Method.
IWLS 2002: 245-250 |
| 19 | | Ken-ichi Kurata,
Christian Saguez,
Gerald Dine,
Hiroshi Nakamura:
Rapid Analysis of Specificity of PCR Product on the Whole Genome.
PDPTA 2002: 246-252 |
| 18 | EE | Hiroshi Nakamura,
Takanori Arai,
Masahiro Fujita:
Formal Verification of a Pipelined Processor with New Memory.
PRDC 2002: 321-324 |
| 17 | EE | Masaaki Kondo,
Motonobu Fujita,
Hiroshi Nakamura:
Software-controlled on-chip memory for high-performance and low-power computing.
SIGARCH Computer Architecture News 30(3): 7-8 (2002) |
| 2001 |
| 16 | EE | Motokazu Ozawa,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya,
Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
ASYNC 2001: 162-172 |
| 15 | | Masahiro Fujita,
Hiroshi Nakamura:
The standard SpecC language.
ISSS 2001: 81-86 |
| 2000 |
| 14 | EE | Masaaki Kondo,
Hideki Okawara,
Hiroshi Nakamura,
Taisuke Boku:
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.
ICCD 2000: 105- |
| 13 | EE | Hiroshi Nakamura,
Masaaki Kondo,
Taisuke Boku:
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.
Intelligent Memory Systems 2000: 15-32 |
| 1999 |
| 12 | EE | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers 48(2): 142-149 (1999) |
| 11 | | S. Aoki,
R. Burkhalter,
K. Kanaya,
T. Yoshié,
Taisuke Boku,
Hiroshi Nakamura,
Yoshiyuki Yamashita:
Performance of lattice QCD programs on CP-PACS.
Parallel Computing 25(10-11): 1243-1255 (1999) |
| 10 | | Kisaburo Nakazawa,
Hiroshi Nakamura,
Taisuke Boku,
Ikuo Nakata,
Yoshiyuki Yamashita:
CP-PACS: A massively parallel processor at the University of Tsukuba.
Parallel Computing 25(13-14): 1635-1661 (1999) |
| 1997 |
| 9 | | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
A Data Alignment Technique for Improving Cache Performance.
ICCD 1997: 587-592 |
| 8 | | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
Improving cache Performance Through Tiling and Data Alignment.
IRREGULAR 1997: 167-185 |
| 7 | EE | Taisuke Boku,
Ken'ichi Itakura,
Hiroshi Nakamura,
Kisaburo Nakazawa:
CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations.
International Conference on Supercomputing 1997: 108-115 |
| 1994 |
| 6 | | Hiroshi Nakamura,
Kisaburo Nakazawa,
Hang Li,
Hiromitsu Imori,
Taisuke Boku,
Ikuo Nakata,
Yoshiyuki Yamashita:
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.
HICSS (1) 1994: 368-377 |
| 1993 |
| 5 | EE | Hiroshi Nakamura,
Taisuke Boku,
Hideo Wada,
Hiromitsu Imori,
Ikuo Nakata,
Yasuhiro Inagami,
Kisaburo Nakazawa,
Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.
International Conference on Supercomputing 1993: 298-307 |
| 1992 |
| 4 | | Kisaburo Nakazawa,
Hiroshi Nakamura,
Hiromitsu Imori,
Shun Kawabe:
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.
SC 1992: 642-651 |
| 1990 |
| 3 | | Hiroshi Nakamura,
Yuji Kukimoto,
Masahiro Fujita,
Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.
CAV 1990: 76-85 |
| 1989 |
| 2 | | Hiroshi Nakamura,
Masaya Nakai,
Shinji Kono,
Masahiro Fujita,
Hidehiko Tanaka:
Logic Design Assistence Using Temporal Logic Based Language Tokio.
LP 1989: 174-183 |
| 1985 |
| 1 | | Masahiro Fujita,
Makoto Ishisone,
Hiroshi Nakamura,
Hidehiko Tanaka,
Tohru Moto-Oka:
Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.
LP 1985: 246-255 |