| 2008 |
|---|
| 47 | EE | James Dardig,
Haralampos-G. D. Stratigopoulos,
Eric Stern,
Mark Reed,
Yiorgos Makris:
A Statistical Approach to Characterizing and Testing Functionalized Nanowires.
VTS 2008: 267-274 |
| 46 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 339-351 (2008) |
| 2007 |
|---|
| 45 | EE | Haralampos-G. D. Stratigopoulos,
Petros Drineas,
Mustapha Slamani,
Yiorgos Makris:
Non-RF to RF Test Correlation Using Learning Machines: A Case Study.
VTS 2007: 9-14 |
| 44 | EE | Sobeeh Almukhaizim,
Yiorgos Makris:
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines.
IEEE Trans. Computers 56(6): 785-798 (2007) |
| 43 | EE | Yiorgos Makris,
Alex Orailoglu:
On the identification of modular test requirements for low cost hierarchical test path construction.
Integration 40(3): 315-325 (2007) |
| 2006 |
|---|
| 42 | EE | Gennette Gill,
Ankur Agiwal,
Montek Singh,
Feng Shi,
Yiorgos Makris:
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.
ASYNC 2006: 46-56 |
| 41 | EE | Feng Shi,
Yiorgos Makris:
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.
ASYNC 2006: 57-67 |
| 40 | EE | Sobeeh Almukhaizim,
Yiorgos Makris:
Berger code-based concurrent error detection in asynchronous burst-mode machines.
DATE 2006: 71-72 |
| 39 | EE | Feng Shi,
Yiorgos Makris:
Testing delay faults in asynchronous handshake circuits.
ICCAD 2006: 193-197 |
| 38 | EE | Andreas G. Veneris,
Yiorgos Makris:
Session Abstract.
VTS 2006: 290-291 |
| 37 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing.
VTS 2006: 406-411 |
| 36 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Concurrent detection of erroneous responses in linear analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 878-891 (2006) |
| 35 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1547-1554 (2006) |
| 2005 |
|---|
| 34 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Generating decision regions in analog measurement spaces.
ACM Great Lakes Symposium on VLSI 2005: 88-91 |
| 33 | EE | Feng Shi,
Yiorgos Makris:
SPIN-PAC: test compaction for speed-independent circuits.
ASP-DAC 2005: 71-74 |
| 32 | EE | Sobeeh Almukhaizim,
Yiorgos Makris:
Concurrent Error Detection in Asynchronous Burst-Mode Controllers.
DATE 2005: 1272-1277 |
| 31 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Constructive Derivation of Analog Specification Test Criteria.
VTS 2005: 395-400 |
| 30 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Nonlinear decision boundaries for testing analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1760-1773 (2005) |
| 29 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
Compaction-based concurrent error detection for digital circuits.
Microelectronics Journal 36(9): 856-862 (2005) |
| 2004 |
|---|
| 28 | EE | Feng Shi,
Yiorgos Makris:
Fault simulation and random test generation for speed-independent circuits.
ACM Great Lakes Symposium on VLSI 2004: 127-130 |
| 27 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
On Concurrent Error Detection with Bounded Latency in FSMs.
DATE 2004: 596-603 |
| 26 | EE | Feng Shi,
Yiorgos Makris:
SPIN-TEST: automatic test pattern generation for speed-independent circuits.
ICCAD 2004: 903-908 |
| 25 | EE | Feng Shi,
Sobeeh Almukhaizim,
Pey-Chang Lin,
Yiorgos Makris:
Compiler-Based Frame Formation for Static Optimization.
ICCD 2004: 466-471 |
| 24 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction.
ISQED 2004: 459-464 |
| 23 | EE | Feng Shi,
Yiorgos Makris:
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits.
ITC 2004: 597-606 |
| 22 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
Cost-Driven Selection of Parity Trees.
VTS 2004: 319-324 |
| 21 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Transactions on Reliability 53(2): 269-278 (2004) |
| 2003 |
|---|
| 20 | EE | Petros Drineas,
Yiorgos Makris:
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees.
DATE 2003: 11164-11167 |
| 19 | EE | Konstantinos Rokas,
Yiorgos Makris,
Dimitris Gizopoulos:
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs.
DFT 2003: 344-351 |
| 18 | EE | Sobeeh Almukhaizim,
Yiorgos Makris:
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code.
DFT 2003: 563-570 |
| 17 | EE | Sobeeh Almukhaizim,
Thomas Verdel,
Yiorgos Makris:
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case.
ICCD 2003: 194-197 |
| 16 | EE | Petros Drineas,
Yiorgos Makris:
Independent Test Sequence Compaction through Integer Programming.
ICCD 2003: 380-386 |
| 15 | EE | Sobeeh Almukhaizim,
Petros Drineas,
Yiorgos Makris:
On Compaction-Based Concurrent Error Detection.
IOLTS 2003: 157 |
| 14 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
An Analog Checker With Input-Relative Tolerance for Duplicate Signals.
IOLTS 2003: 54- |
| 13 | EE | Petros Drineas,
Yiorgos Makris:
Concurrent Fault Detection in Random Combinational Logic.
ISQED 2003: 425-430 |
| 12 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Concurrent Error Detection in Linear Analog Circuits Using State Estimation.
ITC 2003: 1164-1173 |
| 11 | EE | Petros Drineas,
Yiorgos Makris:
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs.
VLSI Design 2003: 167- |
| 10 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.
VTS 2003: 209-218 |
| 2002 |
|---|
| 9 | EE | Yiorgos Makris,
Alex Orailoglu:
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction.
Asian Test Symposium 2002: 134-139 |
| 8 | EE | Petros Drineas,
Yiorgos Makris:
Non-Intrusive Design of Concurrently Self-Testable FSMs.
Asian Test Symposium 2002: 33- |
| 7 | EE | Thomas Verdel,
Yiorgos Makris:
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies.
DFT 2002: 345-353 |
| 2001 |
|---|
| 6 | EE | Yiorgos Makris,
Vishal Patel,
Alex Orailoglu:
Efficient Transparency Extraction and Utilization in Hierarchical Test.
VTS 2001: 246-251 |
| 2000 |
|---|
| 5 | EE | Yiorgos Makris,
Jamison Collins,
Alex Orailoglu:
Fast hierarchical test path construction for DFT-free controller-datapath circuits.
Asian Test Symposium 2000: 185-190 |
| 4 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
VTS 2000: 459-464 |
| 1999 |
|---|
| 3 | EE | Yiorgos Makris,
Alex Orailoglu:
Channel-Based Behavioral Test Synthesis for Improved Module Reachability.
DATE 1999: 283-288 |
| 2 | EE | Yiorgos Makris,
Alex Orailoglu:
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
DFT 1999: 339-347 |
| 1998 |
|---|
| 1 | EE | Yiorgos Makris,
Alex Orailoglu:
DFT guidance through RTL test justification and propagation analysis.
ITC 1998: 668- |
