| 2007 |
|---|
| 9 | EE | Rajiv V. Joshi,
Rouwaida Kanj,
Keunwoo Kim,
Richard Williams,
Ching-Te Chuang:
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
ISLPED 2007: 8-13 |
| 8 | EE | Amin Khajeh Djahromi,
Ahmed M. Eltawil,
Fadi J. Kurdahi,
Rouwaida Kanj:
Cross Layer Error Exploitation for Aggressive Voltage Scaling.
ISQED 2007: 192-197 |
| 7 | EE | Rouwaida Kanj,
Rajiv V. Joshi,
Jayakumaran Sivagnaname,
Jente B. Kuang,
Dhruva Acharyya,
Tuyet Nguyen,
Chandler McDowell,
Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
ISQED 2007: 33-40 |
| 2006 |
|---|
| 6 | EE | Rouwaida Kanj,
Rajiv V. Joshi,
Sani R. Nassif:
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
DAC 2006: 69-72 |
| 5 | EE | Fadi J. Kurdahi,
Ahmed M. Eltawil,
Young-Hwan Park,
Rouwaida Kanj,
Sani R. Nassif:
System-Level SRAM Yield Enhancement.
ISQED 2006: 179-184 |
| 4 | EE | Praveen Elakkumanan,
Jente B. Kuang,
Kevin J. Nowka,
Ramalingam Sridhar,
Rouwaida Kanj,
Sani R. Nassif:
SRAM Local Bit Line Access Failure Analyses.
ISQED 2006: 204-209 |
| 2004 |
|---|
| 3 | EE | Rouwaida Kanj,
Timothy Lehner,
Bhavna Agrawal,
Elyse Rosenbaum:
Noise characterization of static CMOS gates.
DAC 2004: 888-893 |
| 2 | EE | Rouwaida Kanj,
Elyse Rosenbaum:
Critical evaluation of SOI design guidelines.
IEEE Trans. VLSI Syst. 12(9): 885-894 (2004) |
| 2002 |
|---|
| 1 | EE | Rouwaida Kanj,
Elyse Rosenbaum:
A critical look at design guidelines for SOI logic gates.
ISCAS (3) 2002: 261-264 |
