| 2007 |
| 52 | EE | Arijit Mondal,
P. P. Chakrabarti,
Pallab Dasgupta:
Timing Analysis of Sequential Circuits Using Symbolic Event Propagation.
ICCTA 2007: 151-157 |
| 51 | EE | Suchismita Roy,
P. P. Chakrabarti,
Pallab Dasgupta:
Bounded Delay Timing Analysis Using Boolean Satisfiability.
VLSI Design 2007: 295-302 |
| 50 | EE | Sayak Ray,
Pallab Dasgupta,
P. P. Chakrabarti:
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.
VLSI Design 2007: 95-102 |
| 49 | EE | Suchismita Roy,
P. P. Chakrabarti,
Pallab Dasgupta:
Event propagation for accurate circuit delay calculation using SAT.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 48 | EE | Bhaskar Pal,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti:
BUSpec: A framework for generation of verification aids for standard bus protocol specifications.
Integration 40(3): 285-304 (2007) |
| 2006 |
| 47 | EE | Prasenjit Basu,
Sayantan Das,
Pallab Dasgupta,
Partha Pratim Chakrabarti:
Discovering the input assumptions in specification refinement coverage.
ASP-DAC 2006: 13-18 |
| 46 | EE | Ansuman Banerjee,
Bhaskar Pal,
Sayantan Das,
Abhijeet Kumar,
Pallab Dasgupta:
Test generation games from formal specifications.
DAC 2006: 827-832 |
| 45 | EE | Sayantan Das,
Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti:
What lies between design intent coverage and model checking?
DATE 2006: 1217-1222 |
| 44 | EE | Sayantan Das,
Rizi Mohanty,
Pallab Dasgupta,
P. P. Chakrabarti:
Synthesis of system verilog assertions.
DATE Designers' Forum 2006: 70-75 |
| 43 | EE | Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti:
Formal methods for checking realizability of coalitions in 3-party systems.
MEMOCODE 2006: 198 |
| 42 | EE | Diganchal Chakraborty,
P. P. Chakrabarti,
Arijit Mondal,
Pallab Dasgupta:
A Framework for Estimating Peak Power in Gate-Level Circuits.
PATMOS 2006: 573-582 |
| 41 | EE | Samik Das,
P. P. Chakrabarti,
Pallab Dasgupta:
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search.
VLSI Design 2006: 293-298 |
| 40 | EE | Prasenjit Basu,
Sayantan Das,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix,
Roy Armoni:
Design-Intent Coverage - A New Paradigm for Formal Property Verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1922-1934 (2006) |
| 2005 |
| 39 | | Suchismita Roy,
Sayantan Das,
Prasenjit Basu,
Pallab Dasgupta,
Partha Pratim Chakrabarti:
SAT based solutions for consistency problems in formal property specifications for open systems.
ICCAD 2005: 885-888 |
| 38 | EE | Sayantan Das,
Ansuman Banerjee,
Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix:
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.
VLSI Design 2005: 201-206 |
| 37 | EE | Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti:
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.
VLSI Design 2005: 213-218 |
| 36 | EE | Ansuman Banerjee,
Pallab Dasgupta:
The open family of temporal logics: Annotating temporal operators with input constraints.
ACM Trans. Design Autom. Electr. Syst. 10(3): 492-522 (2005) |
| 2004 |
| 35 | EE | Prasenjit Basu,
Sayantan Das,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix:
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
DATE 2004: 668-669 |
| 34 | EE | Sayantan Das,
Prasenjit Basu,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix,
Roy Armoni:
Formal verification coverage: computing the coverage gap between temporal specifications.
ICCAD 2004: 198-203 |
| 33 | EE | Krishnendu Chatterjee,
Pallab Dasgupta,
P. P. Chakrabarti:
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures.
IWDC 2004: 102-113 |
| 32 | EE | Bhaskar Pal,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti:
The BUSpec platform for automated generation of verification aids for standard bus protocols.
MEMOCODE 2004: 119-128 |
| 31 | EE | Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti:
Formal Verification of Modules under Real Time Environment Constraints.
VLSI Design 2004: 103-108 |
| 30 | EE | Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan:
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.
VLSI Design 2004: 109-114 |
| 29 | EE | Krishnendu Chatterjee,
Pallab Dasgupta,
P. P. Chakrabarti:
The power of first-order quantification over states in branching and linear time temporal logics.
Inf. Process. Lett. 91(5): 201-210 (2004) |
| 2003 |
| 28 | EE | Ansuman Banerjee,
Pallab Dasgupta,
Partha Pratim Chakrabarti:
Open computation tree logic with fairness.
ISCAS (5) 2003: 249-252 |
| 27 | | Krishnendu Chatterjee,
Pallab Dasgupta,
P. P. Chakrabarti:
A Branching Time Temporal Framework for Quantitative Reasoning.
J. Autom. Reasoning 30(2): 205-232 (2003) |
| 2002 |
| 26 | EE | Pallab Dasgupta,
Arindam Chakrabarti,
P. P. Chakrabarti:
Open Computation Tree Logic for Formal Verification of Modules.
ASP-DAC 2002: 735-740 |
| 25 | EE | Arindam Chakrabarti,
Pallab Dasgupta,
P. P. Chakrabarti,
Ansuman Banerjee:
Formal verification of module interfaces against real time specifications.
DAC 2002: 141-145 |
| 24 | EE | Pallab Dasgupta,
Arindam Chakrabarti,
P. P. Chakrabarti:
Open Computation Tree Logic for Formal Verification of Modules.
VLSI Design 2002: 735-740 |
| 23 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
Arnab Dey,
Sujoy Ghose,
Wolfgang Bibel:
Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques.
IEEE Trans. Knowl. Data Eng. 14(2): 353-368 (2002) |
| 22 | EE | Anindya C. Patthak,
Indrajit Bhattacharya,
Anirban Dasgupta,
Pallab Dasgupta,
P. P. Chakrabarti:
Quantified Computation Tree Logic.
Inf. Process. Lett. 82(3): 123-129 (2002) |
| 2001 |
| 21 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
Amit Nandi,
Sekar Krishna,
Arindam Chakrabarti:
Abstraction of word-level linear arithmetic functions from bit-level component descriptions.
DATE 2001: 4-8 |
| 20 | EE | S. Sriram,
R. Tandon,
Pallab Dasgupta,
P. P. Chakrabarti:
Symbolic verification of Boolean constraints over partially specified functions.
ISCAS (5) 2001: 113-116 |
| 19 | EE | Jatindra Kumar Deka,
S. Chaki,
Pallab Dasgupta,
P. P. Chakrabarti:
Abstractions for model checking of event timings.
ISCAS (5) 2001: 125-128 |
| 18 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
Jatindra Kumar Deka,
Sriram Sankaranarayanan:
Min-max Computation Tree Logic.
Artif. Intell. 127(1): 137-162 (2001) |
| 2000 |
| 17 | EE | Pallab Dasgupta,
Jatindra Kumar Deka,
Partha Pratim Chakrabarti:
Model checking on timed-event structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 601-611 (2000) |
| 1999 |
| 16 | | Prashanti Das,
Dibyendu Das,
Pallab Dasgupta:
Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems.
HiPC 1999: 143-150 |
| 15 | EE | Partha Pratim Chakrabarti,
Pallab Dasgupta,
Partha Pratim Das,
Arnob Roy,
Shuvendu K. Lahiri,
Mrinal Bose:
Controlling State Explosion in Static Simulation by Selective Composition.
VLSI Design 1999: 226-231 |
| 14 | EE | Jatindra Kumar Deka,
Pallab Dasgupta,
P. P. Chakrabarti:
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.
VLSI Design 1999: 294-299 |
| 13 | EE | Pankaj Chauhan,
Pallab Dasgupta,
P. P. Chakrabarti:
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.
VLSI Design 1999: 324- |
| 1998 |
| 12 | EE | Pallab Dasgupta:
Agreement under Faulty Interfaces.
Inf. Process. Lett. 65(3): 125-129 (1998) |
| 11 | | Dibyendu Das,
Pallab Dasgupta,
Prashanti Das:
A Heuristic for the Maximum Processor Requirement for Scheduling Layered Task Graphs with Coloring.
J. Parallel Distrib. Comput. 49(2): 169-181 (1998) |
| 1997 |
| 10 | | Pallab Dasgupta,
A. K. Majumder,
P. Bhattacharya:
V_THR: An Adaptive Load Balancing Algorithm.
J. Parallel Distrib. Comput. 42(2): 101-108 (1997) |
| 1996 |
| 9 | | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
A New Competitive Algorithm for Agent Searching in Unknown Streets.
FSTTCS 1996: 147-155 |
| 8 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
Searching Game Trees under a Partial Order.
Artif. Intell. 82(1-2): 237-257 (1996) |
| 7 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs.
Inf. Process. Lett. 58(6): 311-318 (1996) |
| 6 | | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
Multiobjektive Heuristic Search in AND/OR Graphs.
J. Algorithms 20(2): 282-311 (1996) |
| 1995 |
| 5 | | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors.
FSTTCS 1995: 22-36 |
| 4 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening".
Artif. Intell. 77(1): 173-176 (1995) |
| 3 | EE | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
Utility of Pathmax in Partial Order Heuristic Search.
Inf. Process. Lett. 55(6): 317-322 (1995) |
| 1994 |
| 2 | | Pallab Dasgupta,
Prasenjit Mitra,
P. P. Chakrabarti,
S. C. De Sarkar:
Multiobjective Search in VLSI Design.
VLSI Design 1994: 395-400 |
| 1 | | Pallab Dasgupta,
P. P. Chakrabarti,
S. C. De Sarkar:
Agent Searching in a Tree and the Optimality of Iterative Deepening.
Artif. Intell. 71(1): 195-208 (1994) |