30. MICRO 1997: Research Triangle Park, North Carolina, USA

• Chih-Chieh Lee, I-Cheng K. Chen, Trevor N. Mudge:
  The bi-Mode Branch Predictor. 4-13
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• Quinn Jacobson, Eric Rotenberg, James E. Smith:
  Path-Based Next Trace Prediction. 14-23
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• Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt:
  Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. 24-33
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• Jared Stark, Paul Racunas, Yale N. Patt:
  Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. 34-43
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• Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin:
  On High-Bandwidth Data Cache Design for Multi-Issue Processors. 46-56
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• Teresa L. Johnson, Matthew C. Merten, Wen-mei W. Hwu:
  Run-Time Spatial Locality Detection and Optimization. 57-64
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• G. P. Jones, Nigel P. Topham:
  A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. 65-70
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• Nigel P. Topham, Antonio González, José González:
  The Design and Performance of a Conflict-Avoiding Cache. 71-80
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• James E. Bennett, Michael J. Flynn:
  Prediction Caches for Superscalar Processors. 81-90
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• David I. August, Wen-mei W. Hwu, Scott A. Mahlke:
  A Framework for Balancing Control Flow and Predication. 92-103
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• Seongbae Park, SangMin Shim, Soo-Mook Moon:
  Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. 104-113
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• Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen:
  Tuning Compiler Optimizations for Simultaneous Multithreading. 114-124
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• Milo M. K. Martin, Amir Roth, Charles N. Fischer:
  Exploiting Dead Value Information. 125-135
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• Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith:
  Trace Processors. 138-148
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• Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
  The Multicluster Architecture: Reducing Cycle Time Through Partitioning. 149-159
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• Roger Espasa, Mateo Valero, James E. Smith:
  Out-of-Order Vector Architectures. 160-170
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• Corinna G. Lee, Derek J. DeVries:
  Initial Results on the Performance and Cost of Vector Microprocessors. 171-182
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• Johnson Kin, Munish Gupta, William H. Mangione-Smith:
  The Filter Cache: An Energy Efficient Memory Structure. 184-193
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• Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, Trevor N. Mudge:
  Improving Code Density Using Compression Techniques. 194-203
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• Darko Kirovski, Johnson Kin, William H. Mangione-Smith:
  Procedure Based Program Compression. 204-213
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• Gary S. Tyson, Todd M. Austin:
  Improving the Accuracy and Performance of Memory Communication Through Renaming. 218-227
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• Chung-Ho Chen, Akida Wu:
  Microarchitecture Support for Improving the Performance of Load Target Prediction. 228-234
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• Andreas Moshovos, Gurindar S. Sohi:
  Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. 235-245
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• Yiannakis Sazeides, James E. Smith:
  The Predictability of Data Values. 248-258
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• Brad Calder, Peter Feller, Alan Eustace:
  Value Profiling. 259-269
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• Freddy Gabbay, Avi Mendelson:
  Can Program Profiling Support Value Prediction? 270-280
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• Kai Wang, Manoj Franklin:
  Highly Accurate Data Value Prediction Using Hybrid Predictors. 281-290
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• Jeffrey Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl, George Z. Chrysos:
  ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors. 292-302
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• Nicholas C. Gloy, Trevor Blackwell, Michael D. Smith, Brad Calder:
  Procedure Placement Using Temporal Ordering Information. 303-313
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• Todd C. Mowry, Chi-Keung Luk:
  Predicting Data Cache Misses in Non-Numeric Applications through Correlation Profiling. 314-320
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• Heng Liao, Andrew Wolfe:
  Available Parallelism in Video Applications. 321-329
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• Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith:
  MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. 330-335
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• F. Jesús Sánchez, Antonio González:
  Cache Sensitive Modulo Scheduling. 338-348
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• Steve Carr, Yiping Guan:
  Unroll-and-Jam Using Uniformly Generated Sets. 349-357
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• Rajiv Gupta, David A. Berson, Jesse Zhixi Fang:
  Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization. 358-368
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